Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby

ABSTRACT

A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

FIELD OF THE INVENTION

This invention pertains to the formation of back end of the line (BEOL)interconnect structures for advanced microelectronic chips of the typeused in microprocessors, microcontrollers, communications, graphics andthe like. In particular, methods pertinent to improving the performanceof SRAM cells in such chips by enabling a higher capacitanceinterconnect environment selectively in the SRAM regions of such chipsare described.

BACKGROUND

Limited by array leakage and read stability, CMOS SRAM cell devicethreshold voltages (VT) have scaled less aggressively than logicrequiring a separate, higher supply voltage (VDD-CELL) to enable higherstatic noise margin (SNM) and read current (IREAD), and lower readcurrent variability, in the presence of increasingly severe, random VTfluctuations in small geometry SRAM cell transistors. However, a secondarray of power supply translates into more input output (I/O)requirements and fewer metal wiring tracks for other chip functions suchas power, global signal and clock distribution—all of which directlyimpact cost. Secondly, higher/dual cell power supplies result in (i)more leakage due to all components from unaccessed Subarrays of large L2caches during active mode and (ii) more switching power, adverselyimpacting battery lifetime for portable applications as well as the costof packaging for high performance desktop and server products.

New circuit techniques were reported in a co-pending applicationYOR9200300292US1 by some of the present authors that enable a single VDDSRAM to operate at logic compatible voltages with a cell read currentand cell static noise margin typically seen with higher/dual VDD SRAMs.The schematic circuit implementations are shown in FIGS. 1 a, 1 b and 2.FIG. 3 shows the physical implementation of the SRAM cell interconnectsschematically where the array of word lines (WL) and the associatedpower lines (PL) are shown. Implemented in a 65 nm CMOS SOI process withno alterations to the CMOS processes and materials or to a conventional,single VT SRAM cell, the voltage across power rails of the selected SRAMcells self-biases to permit a higher-than-VDD voltage during word line(WL) active periods and a lower than 2VT voltage at all other times.Based on circuit simulations data, FIG. 4, this “bootstrapping” has beenshown to increase the supply voltage by about 17% under this circuitimplementation. Bootstrapping the cell row power supply and regulatingthe cell Subarray virtual ground voltage enables the above‘Transregional’ SRAM operation resulting in near-subthreshold datastorage and superthreshold access, lowering total leakage by over 10×and improving IREAD and SNM by 7% and 18% respectively with a total areaoverhead of less than 13%.

It is therefore clear that ‘Transregional’ SRAM operation enables logicVDD compatibility, lower leakage, and higher cell read stability withoutdegradation of performance. The benefits of this bootstrapping effectcan be significantly enhanced over those shown in prior art by enablinga stronger capacitive coupling between the WL that selects a row of SRAMcells and the power line(PL) pair that supply power to that row.Incorporation of a higher k dielectric material between the WL and PLlines in an SRAM subarray, to enable a stronger capacitive couplingbetween WL and PL is a way to achieve this end. However, using a higherk dielectric at other the regions of the chip (areas of logic andinterconnects) is detrimental to chip performance as increasedcapacitance in these regions translates to increased RC delay and henceslower interconnect speeds. In this invention, we teach a structure thatenables higher capacitive coupling in the SRAM cell areas and lowercapacitance elsewhere so as to overcome this problem. Several methods tofabricate such a structure are also taught.

It is therefore an object of this invention to describe a chipinterconnect structure that will enable a hybrid system of inter-metaldielectrics (IMD): a high k or ultra-high k dielectric in theinter-metal gaps between the WL and PL features, FIG. 5, while providinglow k or ultra low k dielectric separating the interconnect lineselsewhere. For the purpose of convenience in the descriptions below wearbitrarily define high k as 7<k<4 and ultra high k as k>7 and low k as4<k<2.0 and ultra low k as k<2. It is further the object of thisinvention to achieve the optimum benefits in the SRAM performancemetrics as outlined above while maintaining the mechanical robustness ofthe chip and the low effective interconnect capacitance to minimizeinterconnect delay elsewhere on the chip. It is further an object ofthis invention to describe methods to fabricate the above describedhybrid interconnect structure.

These and other aspects of our invention are described below in detailalong with the following set of illustrative figures.

DESCRIPTION

FIG. 1. Schematic circuit diagram of a Transregional SRAM implementationshowing PL bootstrapped to be above VDD and with VGND regulated with aPFET diode stack. (Prior art patent application YOR9200300292US1 by someof the present inventors).

FIG. 2. Bootstrap approach shown schematically in circuit implementationform on PL. (Prior art patent application YOR9200300292US1 by some ofthe present inventors).

FIG. 3. Physical implementation of a bootstrap on to a pair of PL lines.(Prior art patent application YOR9200300292US1 by some of the presentinventors).

FIG. 4. Circuit simulations demonstrating Transregional SRAM operationwith the bootstrap using the same insulating material between WL & PL asanywhere else. (Prior art patent application YOR9200300292US1 by some ofthe present inventors).

FIG. 5. Proposed enhanced physical implementation of the bootstrapapproach according to the present invention using higher k dielectricbetween WL and PL tracks and low k dielectric elsewhere in the chip area(not shown).

FIG. 6. Schematic description of the etch back and gap fill integrationscheme (U.S. patent application 200040087135A1 by some of the presetauthors).

FIG. 7. Schematic description of the first inventive method to fabricatethe hybrid SRAM interconnect structure using EBGF and a block outlithography step.

FIG. 8. Schematic description of the second inventive process describedbelow.

FIG. 9. Schematic description of the third inventive process describedbelow.

DETAILED DESCRIPTION OF THE INVENTION

We teach the fabrication of the hybrid structure described above usingan etch back and gap fill (EBGF) integration scheme (U.S. patentapplication 200040087135A1 by some of the preset authors) or variantsthereof.

In the EBGF scheme, schematically shown in FIG. 6, the interconnectwires 500 are first fabricated in a dense dielectric medium 600(typically a material of higher k such as oxide, SiCOH, dense spin onglasses and the like), FIG. 6 a. The dense dielectric is then etchedfrom between the inter-line gaps using the lines themselves as an etchmask to produce the structure shown in FIG. 6 b. Then a lower kdielectric (typically a low k or very low k dielectric material 550often porous so as to have k values as low as 1.6) is deposited so as tooverfill the etched recesses as shown in FIG. 6 c. The structure is thenplanarized by a chem-mech polish (CMP) process and capped with apassivation dielectric 650 resulting in an EBGF structure shown in FIG.6 d. The dense dielectric 600 is considered a support dielectric and isused to provide mechanical robustness as the low k IMD 550 is usuallymechanically fragile.

In the first inventive method, depicted schematically in FIG. 7, theEBGF method is used in conjunction with a simple block out lithographystep that protects the SRAM cell regions where WL and PL lines arelocated with a photoresist mask so that the dense dielectric is left intact between these lines. FIG. 7.1 shows the top down view of thestructure after the standard build in a dense and robust BEOL dielectric600. Interconnect lines are not shown for the sake of simplicity.Following this, as shown in FIG. 7.2, the SRAM cell regions areprotected by photoresist 100 using an exposure with a blockout mask.Following this, as shown in FIG. 7.3, the robust BEOL dielectric isetched back in the regions not protected by the blockout mask andfollowed by a resist strip. Finally, the etched back regions are gapfilled and planarized with a dielectric 550 with a lower k than therobust BEOL dielectric 600 as shown in FIG. 7.4. For example, themechanically robust BEOL dielectric 600 can be selected from the groupcomprising silicon oxide, fluorinated silicon oxide, organosilicatedielectrics comprising silicon, carbon, oxygen and hydrogen. The gapfill dielectric 550 can be porous or dense versions of organosilicatesand organic dielectrics such as polyimides and polyarylene ethers andporous silica with k<2.5 and preferably even lower than 2. Additionally,regions such as the chip kerf sites, bond or probe pads and the dicingchannels can also be protected by the block out lithography to preservethe support dielectric to prevent dicing and bonding induced cracks. Theblock out mask and the associated lithography can be of fairly relaxedin ground rules compared to the minimum ground rule of the technologyused to fabricate the cells and thus will not be significant cost adder.In this manner, it is possible to make mechanically robust hybridstructures wherein the k of the IMD in the WL/PL gaps is as high as 4and the k of the IMD in the remaining interconnect regions is as low as1.6. This enables an increased bootstrapping voltage in the SRAM cellsenabled by the higher Cc values from the high k material whilemaintaining the high speed (low capacitance) for the interconnect wiringelsewhere on the chip.

In the second inventive method, we propose the fabrication of theinterconnect structures with a low k dielectric 700 (such as porous anddense versions of organosilicates and organic dielectrics such aspolyimides and polyarylene ethers and porous silica), protecting all theregions EXCEPT the WL/PL gap areas with a block out resist mask 100,etching the low k dielectric from between the WL/PL lines and gapfilling and planarizing with a high k dielectric 750. This process flowis shown schematically in FIG. 8 (again omitting the interconnect linesfor simplicity). In this case it is possible to gap fill with very highk materials such as titania, zirconia, hafnia and their silicates,barium strontium titanate, barium zirconium titanate and the like whichcan be deposited by sol gel processing using metal alkoxide solutions,for example. k values as high as 20-40 are possible in these filmssignificantly increasing the capacitance attainable between WL and PL.The overall interconnect capacitance and mechanical robustness will bedetermined by the low k dielectric used to fabricate the originalstructure before EBGF.

In the third inventive method, shown schematically in FIG. 9, theinterconnects are fabricated using a robust support dielectric 600 witha moderate k, typically in the 2.5 to 4.0 range, FIG. 9.1(note:interconnect lines are omitted for simplicity of illustration). Thisrobust support dielectric 600 can be selected from the group comprisingsilicon oxide, fluorinated silicon oxide, organosilicate dielectricscomprising silicon, carbon, oxygen and hydrogen. In the first block outlithography, only the WL and PL regions of the SRAM areas are exposedwhile the remaining area is blocked out with a photoresist pattern 100as shown in FIG. 9.2. A first etch back of the robust support dielectric600 (FIG. 9.3) is performed followed by a gap fill with high k or ultrahigh k dielectrics 750 as in the first variant above followed by CMPplanarization, FIG. 9.4. Dielectric 750 can thus be selected from thegroup comprising very high k materials such as titania, zirconia, hafniaand their silicates, barium strontium titanate, barium zirconiumtitanate and the like which can be deposited by sol gel processing usingmetal alkoxide solutions, for example. Next, a second block outphotoresist pattern 110 is formed that protects all the SRAM WL/PLregions and the dicing channels and bond pads, FIG. 9.5. An etch back ofthe robust support dielectric 600 in the regions not protected by theblock out pattern 110 (FIG. 9.6) followed by gap fill with low k orultra low k dielectric 550 and planarization leads to interconnect areaswhich are very low in capacitance and hence wiring delay, FIG. 9.7.Dielectric 550 can be selected from the group comprising porous or denseversions of organosilicates and organic dielectrics such as polyimidesand polyarylene ethers and porous silica with k <2.5 and preferably evenlower than 2. The net structure of FIG. 9.7 combines the mechanicalrobustness afforded by the robust support dielectric 600, significantlyreduced interconnect delay enabled by the ultra low k dielectric gapfill 550, and the very large capacitive coupling in the SRAM cellregions achieved through the high k or ultra high k gapfill dielectric750 in that region. The cost of this variant is likely to be slightlymore than the other two variants due to the additional steps requiredbut a higher level of overall performance is achieved and will bejustified where a cost premium for higher performance is acceptable.

In the fourth inventive method the low k or ultra low k IMD regions inthe SRAM cell area alone are modified using a suitable exposure methodselected from ion implantation, photon irradiation, chemicalinfiltration from liquid, vapor or supercritical fluid based deliverymedia followed by an optional thermal annealing. The base interconnectstructure itself can be fabricated by the standard dual damascenetechnique or the EBGF technique as described earlier. Following thebuild of the interconnect structure, a block out lithography isperformed to protect all the areas other than the SRAM cell area with aphotoresist. Then the modification process is carried out that enablesthe conversion of the IMD to a higher k material. The block out resistis stripped and the process of additional layer build is continued withthe dielectric modification step for the SRAM area included inadditional interconnect levels as needed.

The structures resulting from the above described inventive methods havethe higher interconnect capacitance in the cell areas of the SRAMdesirable for the low voltage operation and the low to ultra lowinterconnect capacitance in the other areas desirable for high speedsignal propagation and low interconnect power dissipation. Further, theyincorporate a mechanically robust IMD in the dicing channels, bond padsand under all the interconnect lines thereby providing superior chiprobustness.

1. Independent Structure Claim: An interconnect structure comprising amultitude of conductors disposed atop a first dielectric wherein thespaces between a first subset of said multitude of conductors isoccupied by a second dielectric and the spaces between a second subsetof said multitude of conductors is occupied by a third dielectric.
 2. Astructure according to claim 1 wherein said multitude of conductors areinterconnect wires comprising a conductive barrier liner and a higherconductivity fill material.
 3. A structure according to claim 1 whereinsaid first dielectric is a mechanically robust dielectric selected fromthe group comprising silicon oxide, fluorinated silicon oxide,organosilicate dielectrics comprising silicon, carbon, oxygen andhydrogen.
 4. A structure according to claim 1 wherein said seconddielectric is selected from the group comprising dielectrics depositedby spin coating or plasma enhanced chemical vapor deposition andselected from the group comprising silicon oxide, fluorinated siliconoxide, titania, zirconia, hafnia and their silicates, barium strontiumtitanate, barium zirconium titanate and the like.
 5. A structureaccording to claim 1 wherein said third dielectric is selected from thegroup comprising porous and dense versions of organosilicates andorganic dielectrics such as polyimides and polyarylene ethers and poroussilica.
 6. A structure according to claim 1 wherein said first subset ofconductors are interconnect wires located within the SRAM portion of amicroelectronic chip.
 7. A structure according to claim 6 wherein saidfirst subset of conductors comprises the word and power lines of an SRAMcell.
 8. A structure according to claim 1 wherein said first dielectricis also disposed in the dicing channels and under bonding and test padsin the chip.
 9. A structure according to claim 1 wherein said secondsubset of conductors are located in regions other than the SRAM cellsand serve to interconnect different regions on the chip.
 10. A structureaccording to claim 1 wherein said various dielectrics are depositedusing a method selected from spin coating and curing, sol gelprocessing, chemical vapor deposition, plasma assisted chemical vapordeposition, physical vapor deposition, and atomic layer deposition. 11.The structure according to claim 1 wherein said conductive barriermaterial is selected from the group comprising tantalum andtitanium,nitrides and siliconitrides of tantalum and titanium andcombinations thereof.
 12. The structure according to claim 1 whereinsaid higher conductivity filler material is selected from the groupcomprising copper, aluminum, gold, silver and combinations thereof. 13.The structure according to claim 1 wherein said structure is amechanically robust microelectronic chip with a high interconnectcapacitance in the SRAM regions and low interconnect capacitance in theother interconnect regions.
 14. (Independent Claim: Method 1: Build inrobust IMD, EBGF ULK) A method to fabricate a hybrid interconnectstructure comprising the steps of: depositing a first dielectric andpatterning trenches and vias in said first dielectric on a substrate;filling said trenches and vias with a conductive barrier and a higherconductivity fill material to form interconnect wiring structures;forming a block out resist pattern in a first region of the substrate toexpose only a first subset of said interconnect structures; etching saidfirst dielectric from between said first set of interconnect wireslocated in said first region; and filling the gaps between said firstset of interconnect wires with a second dielectric and planarizing it toform a coplanar structure.
 15. The method according to claim 14 whereinsaid first dielectric is selected from the group comprising siliconoxide, fluorinated silicon oxide, organosilicate dielectrics comprisingsilicon, carbon, oxygen and hydrogen.
 16. The method according to claim14 wherein said conductive barrier material is selected from the groupcomprising tantalum and titanium, nitrides and siliconitrides oftantalum and titanium and combinations thereof.
 17. The method accordingto claim 14 wherein said higher conductivity fill material is selectedfrom the group comprising copper, aluminum, gold, silver andcombinations thereof.
 18. The method according to claim 14 wherein saidsubstrate is a microelectronic chip comprising at least logic blocks,SRAM cells, bond and test pads and dicing channels.
 19. The methodaccording to claim 18 wherein said first region consists of all theregions other than the SRAM cells, dicing channels and the areas usedfor bond and test pads.
 20. The method according to claim 14 whereinsaid etching of said first dielectric is achieved by a process selectedfrom plasma etching, reactive ion etching, ion milling, laser etchingand wet etching.
 21. The method according to claim 14 wherein saidsecond dielectric is selected from the group comprising porous and denseversions of organosilicates and organic dielectrics such as polyimidesand polyarylene ethers and porous silica.
 22. The method according toclaim 14 wherein said planarization of said second dielectric isachieved by chemical mechanical polishing, reactive ion etching or acombination thereof.
 23. The method according to claim 14 wherein thesteps are repeated to produce a multilevel hybrid interconnectstructure.
 24. (Method 2: ULK/LK first and UHK next) The methodaccording to claim 14 wherein said first dielectric is a low k or ultralow k dielectric selected from the group comprising porous and denseversions of organosilicates and organic dielectrics such as polyimidesand polyarylene ethers and porous silica.
 25. The method according toclaim 24 wherein said first region comprises only the SRAM cells on amicroelectronic chip.
 26. The method according to claim 24 wherein saidsecond dielectric is a high k dielectric selected from the groupcomprising silicon oxide, fluorinated silicon oxide, titania, zirconia,hafnia and their silicates, barium strontium titanate, barium zirconiumtitanate and the like.
 27. (Method 3: Build in robust IMD/EBGF UHK/EBGFULK) A method of fabricating a hybrid interconnect structure comprisingthe steps of: depositing a first dielectric and patterning trenches andvias in said first dielectric on a substrate; filling said trenches andvias with a conductive barrier and a higher conductivity fill materialto form interconnect wiring structures; forming a first block out resistpattern to expose only a first set of interconnects in a first region ofthe substrate; etching said first dielectric from between said first setof interconnect wires located in said first region and stripping thephotoresist; filling the etched gaps between said first set ofinterconnect wires with a second dielectric and planarizing it to form acoplanar structure; forming a second blockout photoresist pattern thatexposes a second region of the substrate comprising a second set ofinterconnects; etching said first dielectric from between said secondset of interconnects and stripping the photoresist; and filling theetched gaps between said second set of interconnects with a thirddielectric and planarizing to form a coplanar structure.
 28. A methodaccording to claim 27 wherein said substrate is a microelectronic chipcomprising at least logic blocks, SRAM cells, bond and test pads anddicing channels.
 29. A method according to claim 27 wherein said firstset of interconnects are locate din the SRAM cell area of said chip. 30.A method according to claim 27 wherein said first dielectric is selectedfrom the group comprising silicon oxide, fluorinated silicon oxide,organosilicate dielectrics comprising silicon, carbon, oxygen andhydrogen.
 31. A method according to claim 27 wherein said seconddielectric is selected from group comprising titania, zirconia, hafniaand their silicates, barium strontium titanate, barium zirconiumtitanate and the like.
 32. A method according to claim 27 wherein saidsecond region comprises all the chip area except the SRAM cells, dicingchannels and the bond and test pads.
 33. A method according to claim 27wherein said third dielectric is selected from the group comprisingporous and dense versions of organosilicates and organic dielectricssuch as polyimides and polyarylene ethers and porous silica.
 35. Themethods according to claims 14, 24 and 27 wherein said hybridinterconnect structure produced thereby is a mechanically robustmicroelectronic chip with a high interconnect capacitance in the SRAMregions and low interconnect capacitance in the other interconnectregions.
 36. A structure according to claim 1 wherein the highercapacitance in the SRAM cells is utilized to enable higher power supplyvoltage thereby increasing the static noise margin and reduced leakagein the SRAM cells.
 37. A structure according to claim 1 wherein thehigher capacitance in the SRAM cells is utilized to enable higher powersupply voltage thereby leading to the use of a single power supplyvoltage for both logic and SRAM regions of a microelectronic chip.
 38. Amethod of modifying an interconnect structure fabricated according toclaim 14 by: protecting all areas other than the SRAM cell area with ablock out resist pattern; treating the exposed SRAM cell region by amethod selected from ion implanation, photon irradiation, chemicalinfiltration from liquid, vapor or supercritical fluid media thermalannealning and combinations thereof; resulting in the modification ofthe intermetal dielectric in said SRAM cell area to a higher dielectricconstant so as to enable higher capacitive coupling between theinterconnect lines in said SRAM cell area; and stripping the blockoutphotoresist from the surface.
 39. A method of fabricating a hybridinterconnect structure comprising the steps of: depositing a firstdielectric and patterning trenches and vias in said first dielectric ona substrate; filling said trenches and vias with a conductive barrierand a higher conductivity fill material to form interconnect wiringstructures; forming a block out resist pattern in a first region of thesubstrate to expose only a first subset of said interconnect structures;treating said first subset of said interconnect structures by a methodselected from ion implanation, photon irradiation, chemical infiltrationfrom liquid, vapor or supercritical fluid media, thermal annealing andcombinations thereof; resulting in the modification of the said firstdielectric in said exposed area to convert it into a second dielectricwith a higher dielectric constant so as to enable higher capacitivecoupling between the interconnect lines in said exposed region; andstripping the blockout photoresist from the surface.
 40. A methodaccording to claim 39 wherein said first dielectric is selected from thegroup comprising porous and dense versions of organosilicates andorganic dielectrics such as polyimides and polyarylene ethers and poroussilica.
 41. A method according to claim 39 wherein said conductivebarrier material is selected from the group comprising tantalum andtitanium, nitrides and siliconitrides of tantalum and titanium andcombinations thereof.
 42. A method according to claim 39 wherein saidhigher conductivity fill material is selected from the group comprisingcopper, aluminum, gold, silver and combinations thereof.
 43. A methodaccording to claim 39 wherein said exposed first subset of interconnectsare part of the SRAM cell region of a microelectronic chip.
 44. Themethods according to claims 14, 24, 27 and 39 that result in amicroelectronic chip with a mechanically robust hybrid interconnectstructure and operating with a higher static noise margin and reducedleakage SRAM cells.
 45. The methods according to claims 14, 24, 27 and39 that result in a microelectronic chip with a mechanically robusthybrid interconnect structure and capable of operating with a singlepower supply voltage for both the SRAM and logic cells in said chip.